Modern integrated circuit (IC) designs are often required to provide high speed operation whilst also having low power consumption. In order to provide such opposing requirements, it is known to implement techniques such as clock gating in order to reduce the dynamic power dissipation of an IC device.
Clock gating is a well-known technique used in many synchronous circuits, and enables dynamic power dissipation to be reduced by adding additional components to a circuit to ‘prune’ the clock tree. Such pruning disables the redundant hardware toggling, including, but not limited to, circuit clock tree, hardware registers and other clock dependent devices. When not being switched, the switching power consumption goes to zero, and only leakage currents are incurred.
An important design consideration when implementing a clock gating architecture is the added power requirements of the additional clock gating components, and the impact this can have on the overall power consumption of the IC device. Implementing clock gating on portions of an IC device that would not benefit significantly from clock gating in terms of reduced power consumption may in fact result in the power requirements for the additional clock gating components therefor being greater than the power reductions achieved thereby. Thus, such clock gating may actually increase the power consumption of the IC device. However, an over cautious clock gating implementation will result in sub-optimal power reductions for the IC device, thereby making it more difficult to achieve low power consumption requirements.
In order to maximise the effectiveness of a clock gating architecture, it is necessary to identify those registers of the IC device that would most benefit from clock gating. However, with current electronic design automation (EDA) tools, it is difficult to identify such registers early in the design cycle, and typically impractical to wait until later stages. In particular, for techniques implemented within current synthesis tools, it is difficult to predict the efficiency of a clock gating implementation. Accordingly, it is difficult to achieve an optimally efficient and effective clock gating architecture using current EDA tools.